Backend Engineer, Full Chip Layout

NVIDIA is looking for best-in-class full chip layout Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.What You Will Be DoingFull Chip Layout implementation and analysis of partition groups / top-level according to specifications, under challenging constraints, targeting for the area, route and integration.Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex layout and congestion problems.Daily work involves all aspects of layout implementation and analysis - DRC, LVS, ANT for partition groups and full chip level.Taking part inflows development.What We Need To SeeB.SC. in Electrical Engineering/Computer Engineering.4-6 years of experience as BE/LO engineer.Ability to quickly adapt to new technology and go deep into new areasStrong communication skillsGreat teammate.Drive new solutions based on any issues that ariseWays To Stand Out From The CrowdKnowledge in physical design flows and methodologies (PNR, STA, physical verification).Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!JR1995719