Chief Research Scientist

Chief Scientist – Computing Systems Research | ZurichWe are looking for a Chief Scientist to lead advanced research in computing architecture, AI systems, and hardware-software co-design at our Zurich-based research lab.This role sits within a leading R&D center focused on chip architecture, computing clusters, interconnects, memory subsystems, and AI frameworks. The lab includes over 70 researchers, 50 of whom hold PhDs, and collaborates globally with academia and industry. The team drives fundamental innovation in scalable and efficient computing for next-generation AI workloads.What You’ll DoLead research in next-generation computing architectures, AI accelerators, and general-purpose processors.Anticipate emerging trends and define key research challenges that shape future computing performance and efficiency.Oversee architecture design, performance modeling, and simulation across multiple workloads and hardware targets.Guide research into design space exploration, 3D packaging, interconnects, reliability, and wafer-scale computing.Inspire a team of senior researchers to pursue high-impact, differentiated technical paths.Represent the lab in conferences and academic collaborations, sharing insights and influencing industry direction.Build strategic partnerships with universities and research institutions to extend collaboration and visibility.Ensure consistent delivery of publications, patents, and technical breakthroughs with measurable real-world impact.What We’re Looking ForPhD in Computer Science, Electrical Engineering, or a related field.15+ years of R&D experience in computing architecture, including senior leadership.Deep understanding of AI computing, including LLMs, foundation models, and multimodal systems.Strong publication record (h-index ≥ 30) and contributions to top-tier conferences or patents.Proven ability to lead multi-disciplinary research teams and influence high-level technical decisions.Excellent communication and collaboration skills in both academic and corporate settings.Preferred:Experience with SoC, microarchitecture, and memory design.Proficiency in workload analysis, mapping, and software-hardware co-design.Familiarity with chip manufacturing processes and packaging.