Design Verification Engineer

ResponsibilitiesDefine and implement block/IP/SoC verification plans, build verification test benches to enable block/IP/sub-system/SoC level verificationDevelop functional tests based on verification test planDrive Design Verification to closure based on defined verification metrics on test plan, functional and code coverageDebug, root-cause and resolve functional failures in the design, partnering with the Design teamCollaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design qualityMinimum QualificationsBachelor's degree in Electrical Engineering, Computer Science or other technically related fields3+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog/UVM based methodologiesExperience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environmentsExperience in architecting and implementing Design Verification infrastructure and executing the full verification cyclePreferred QualificationsMaster’s degree in Electrical Engineering, Computer Science or other technically related fields.Experience in development of UVM based verification environments from scratchExperience with IP or integration verification of high-speed interfaces like PCIe, UCIe, DDRExperience with verification of ARM/RISC-V based sub-systems or SoCsExperience with Chisel is a plusStrong Python programming skillsGood communication skillsContactrecruit@furiosa.ai