Mixed Signal Verification Engineer

Experience: 5 - 8 YearsOn-site in Austin, TX, five days a week. Mandatory Requirement5+ years of total experienceExperience in Behavioural Modelling (BM) of Analog design for digital verificationExperience in Verilog/System Verilog codingExperience in Virtuoso Schematics toolsExperience in UVMVerification Methodologies and Tools: Familiarity with verification methodologies and tools, including simulators, waveform viewers, execution automation, and coverage collection. Proven experience in developing scalable and portable test cases. Collaborative Environment: Ability to verify Analog/mixed-signal designs in a collaborative team environment.

About The PositionFor an exciting, well-funded start-up, developing leading-edge technology of the next generation of high-speed communication, we are looking for a mixed-signal verification engineer. Requirements5+ years of total experience Experience in Behavioural Modelling (BM) of Analog design for digital verification Knowledge in Mixed Signals dynamic Verification using chip digital design tools [no AMS] Experience in Verilog/SystemVerilog coding Experience in Virtuoso Schematics tools Basic knowledge in Analog design Preferred QualificationsExperience in UVM Experience in both Synopsys and Cadence tools is an advantage Skills:

mixed signal,digital verification,design verification testing,coverage collection,uvm,virtuoso schematics,system verilog,mixed signals verification,execution automation,universal verification methodology (uvm),signal,simulation tools,waveform viewing,behavioural modelling,analog design,verilog