SoC Physical Design Engineer

About the Role:We are seeking a talented and experienced Physical Design Engineer to join our team and play a key role in the development of our next-generation ASICs. You will be responsible for the physical implementation of complex designs, ensuring they meet performance, power, and area targets while adhering to rigorous design rules and verification procedures.Responsibilities:● ASIC physical implementation by using automatic place and route tools● Floor planning, powerplan synthesis, clock tree synthesis, timing closure, routing, and post-route optimization● Physical verification signoff including DRC, LVS, ERC, Antenna and ESD● Coordinate cross-site communication and coordination among internal supporting groupsQualifications:Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field.Minimum 2 years of experience in physical design of ASICs or complex FPGAs.Strong familiarity with Cadence Innovus or Synopsys Fusion Compiler flow.Proven expertise in timing closure techniques, IR drop analysis, and physical verification procedures.Excellent communication, collaboration, and problem-solving skills.Ability to work independently and as part of a cross-functional team.Strong written and verbal English communication skills.Benefits:Competitive salary and benefits package.Opportunity to work on cutting-edge projects and technologies.Collaborative and supportive work environment.Continuous learning and development opportunities.Career growth potential within a rapidly growing company.Growth Opportunities:Candidates with 8 years or more experience will be considered for senior manager/technical lead positions.Candidates with less experience will be considered for junior positions with the opportunity to grow and learn.𝐹𝑎𝑟𝑎𝑑𝑎𝑦 𝑇𝑒𝑐ℎ𝑛𝑜𝑙𝑜𝑔𝑦 𝑖𝑠 𝑎𝑛 𝑒𝑞𝑢𝑎𝑙 𝑜𝑝𝑝𝑜𝑟𝑡𝑢𝑛𝑖𝑡𝑦 𝑒𝑚𝑝𝑙𝑜𝑦𝑒𝑟. 𝑊𝑒 𝑐𝑒𝑙𝑒𝑏𝑟𝑎𝑡𝑒 𝑑𝑖𝑣𝑒𝑟𝑠𝑖𝑡𝑦 𝑎𝑛𝑑 𝑎𝑟𝑒 𝑐𝑜𝑚𝑚𝑖𝑡𝑡𝑒𝑑 𝑡𝑜 𝑐𝑟𝑒𝑎𝑡𝑖𝑛𝑔 𝑎𝑛 𝑖𝑛𝑐𝑙𝑢𝑠𝑖𝑣𝑒 𝑒𝑛𝑣𝑖𝑟𝑜𝑛𝑚𝑒𝑛𝑡 𝑓𝑜𝑟 𝑎𝑙𝑙 𝑒𝑚𝑝𝑙𝑜𝑦𝑒𝑒𝑠.