南京 IC验证工程师

该职位来源于猎聘 base Nanjing Responsibilities: Work with algorithm team and design engineers to fully understand the assigned functional blocks and develop test plan based on the architecture of ASIC. Implement test benches and test cases with UVM methodology. Responsible for functional verification on block and full chip level, work with design engineers to achieve design objectives. Conduct and maintain verification methodologies such as regression, code coverage and functional coverage analysis. Participate in RTL and post-layout gate level simulation with SDF back-annotation. Participate in pre-silicon validation using FPGA platform, and post-silicon bring up on EVB. Requirements: MSEE and related with 1-5 years relevant verification experience. Familiar with System Verilog and advance UVM/VMM/OVM methodologies. Knowledge of OOPs concepts and C++. Verification experience with mixed signal design and C/SystemC/C++ co-simulation environment is a plus. Domain knowledge in networking ASICs, such as Ethernet PCS/PMA layer or higher layer in IP stack is definitely a plus. Experienced in one or more scripting languages, such as Perl, TCL, Python and Makefile. Good English communication and documentation skill.福利待遇: 1、 期权激励； 2、五险一金，享有国家规定的法定节假日及带薪年假（年假、婚假、产假、病假）等待遇； 3、周末双休，弹性工作时间； 4、定期团建，下午茶，过节礼品，团队聚餐，生日蛋糕，年度体检； 5、公司提供单身公寓，环境好； 6、办公环境舒适，地铁10号线直达，附近多个公交站点，交通十分便利。