UST

Senior STA Engineer

Posted: 20 minutes ago

Job Description

Job Description:Has done timing sign-off including timing margin calculations independently on SOC level.Experience in handling STA of multi-power domain designsSTA flow enhancement, abstraction with bottleneck identificationProficient in design margins and SDC constructsTAT reduction in multi-mode, multi power domain/designsGenerate timing ECOs for Physical designDrive ambitious schedules and enables dependent teams to accomplishProficient with EDA tools from Synopsys/CadenceExcellent analytical & communication skillShow ability to collaborate in multi-functional environment, cross-site or cross-time zoneProficient in Tcl and Perl or other scripting relevant language is a plusStrong in STA fundamentals6-10 years of relevant experience

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